1. Field of the Invention
The present invention relates to a semiconductor device and to a method of fabricating the same. More particularly, the present invention relates to a structure of trench isolation and a method of fabricating the same.
2. Description of the Related Art
As semiconductor devices become more highly integrated, aspect ratios correspondingly increase for device isolation. A problem that occurs in semiconductor devices having high aspect ratios is that a void may be generated in a filling material layer used for filling a trench having a high aspect ratio. To eliminate this problem, a process for filling a trench using a multi-layered structure has been developed. In that process, the aspect ratio of the trench is reduced using a spin on glass (SOG) layer having a superior filling characteristic to fill a lower region of the trench, and then, an upper region of the trench is filled with a high density plasma (HDP) oxide layer or the like.
FIGS. 1 through 3 illustrate cross-sectional views for explaining a conventional method of forming a structure of trench isolation using an SOG layer.
Referring to FIG. 1, a trench mask pattern 35 is formed to define an isolation region on a semiconductor substrate 10. A pad oxide pattern 20, a polish stop pattern 30 and a hard mask pattern (not illustrated) are sequentially stacked to form the trench mask pattern 35. The semiconductor substrate 10 is etched using the trench mask pattern 35 as an etch mask to simultaneously form a first trench 41 and a second trench 42. The first trench 41 has an aspect ratio of at least 4 or more, and cannot therefore be filled with a conventionally used isolation layer. The second trench 42, however, has an aspect ratio of 4 or less, and therefore can be filled with an isolation layer using conventional techniques.
Using a spin coating technique, an SOG layer 50 is formed on the entire surface of a semiconductor substrate where the first and second trenches 41 and 42 are formed. More specifically, the SOG layer 50 is coated in a liquid state on the resultant semiconductor substrate, and the semiconductor substrate is rotated. Thus, even a narrow gap region, such as the first trench 41, is filled with the SOG layer 50 to form a planarized top surface. Then, a thermal process is performed to evaporate a solvent contained in the SOG layer 50. After the thermal process, a curing process, which is thermal process, is performed for forming a dense layer by oxidizing silicon atoms contained in the SOG layer 50. Thus, the SOG layer 50 has characteristics of an oxide layer.
However, although the thermal process and the curing process densify the SOG layer 50 in the second trench 42, the SOG layer 50 in the first trench 41 cannot be made uniformly dense because of the high aspect ratio of the first trench 41. Because of this difference in densification, the SOG layer 50 is thinner at a center than at an edge in the trench 42, which has a wide gap region. This phenomenon becomes more pronounced when the SOG layer 50 is thinly formed.
Also, an SOG layer having a low density has a faster etching rate than an SOG layer having a high density. Further still, although the SOG layer 50 undergoes the densification process, in the oxide-etching recipe, the SOG layer 50 has a faster etch rate as compared to that of a conventional oxide layer.
Referring to FIG. 2, the SOG layer 50 is entirely etched to form a first SOG pattern 51 and a second SOG pattern 52, which fill lower regions of the first and second trenches 41 and 42, respectively. But, since the first and second SOG patterns 51 and 52 have faster etching rates than a conventional oxide layer, when forming an isolation pattern with only the patterns 51 and 52, the patterns 51 and 52 are more rapidly etched than the pad oxide pattern 20 in a subsequent process of removing the pad oxide pattern 20. This results in a problem that top surfaces of the first and second SOG patterns 51 and 52 are lower than a top surface of the semiconductor substrate 10. Thus, it is not preferable to form an isolation pattern with only the first and second SOG patterns 51 and 52. It is preferable to form the first and second SOG patterns 51 and 52 to have top surfaces that are lower than that of the semiconductor substrate 10, and then form an upper isolation layer on the resulting structure. The upper isolation layer is preferably formed of an HDP oxide layer or an undoped silicate glass (USG) layer. The upper isolation layer is preferably planarization-etched until the polish stop pattern (30 of FIG. 1) is exposed, to form an upper isolation pattern 60. The exposed polish stop pattern 30 is removed to expose the pad oxide pattern 20.
However, the SOG layer having a low density is more rapidly etched than the SOG layer having a high density. Thus, in the etching process for forming the first and second SOG patterns 51 and 52, an SOG layer 50 filling the second trench 42 is slowly etched in comparison with the SOG layer 50 filling the first trench 41. This results in a top surface of the second SOG pattern 52 being higher than top surfaces of the first SOG pattern 51 and the semiconductor substrate 10.
The first SOG pattern 51 is formed from a material layer for reducing the aspect ratio of the first trench 41. Thus, through the etching process with respect to the SOG layer 50, the first trench 41, in which the SOG pattern 51 is formed, should have a depth such that the first trench 41 may be filled with the upper isolation pattern 60 without a void being formed therein. Therefore, it is not preferable to over-etch the SOG layer 50 in order to make the top surface of the second SOG pattern 52 lower than that of the semiconductor substrate 10.
Referring to FIG. 3, the pad oxide pattern (20 of FIGS. 1 and 2) is removed to expose the top surface of the semiconductor substrate 10. As explained with reference to FIG. 2, the second SOG pattern 52 has a faster etching rate than both the upper isolation pattern 60 and the pad oxide pattern 20, and further has a top surface that is higher than that of the semiconductor substrate 10. Thus, during the etching process for removing the pad oxide pattern 20, the second SOG pattern 52 is etched more rapidly than the upper isolation pattern 60. Consequently, a groove 99 in the resulting second SOG pattern 53 is formed between the resultant upper isolation pattern 61 and the semiconductor substrate 10. The groove 99, in which the second SOG pattern 52 has been etched, results in a bridge of a gate pattern in a subsequent process.
It is a feature of an embodiment of the present invention to provide a method of forming a structure of trench isolation, in which a trench having a narrow gap is filled with a multi-layered structure including an SOG layer.
It is another feature of an embodiment of the present invention to provide a structure of trench isolation having a multi-layered structure.
A feature of an embodiment of the present invention is directed to a method of forming a structure of trench isolation in which an SOG layer is removed in a wide trench that may be filled by a conventional method. In this method of the present invention, a first trench and a second trench are formed in a first region and a second region of a semiconductor substrate, respectively. Preferably, the first and second regions of the semiconductor substrate are a cell array region and a peripheral circuit region, respectively. A lower isolation pattern is formed to fill a lower region of the first trench, and then, an upper isolation pattern is formed to fill the second trench, and an upper region of the first trench.
In order to form the first and second trenches, a pad oxide pattern and a polish stop pattern are sequentially stacked on the semiconductor substrate. Then, the semiconductor substrate is etched using the polish stop pattern as an etch mask. Preferably, the second trench is formed to be wider than the first trench. After forming the first and second trenches, a nitride liner may be further formed on an entire surface of the semiconductor substrate including the first and second trenches.
The lower isolation pattern may be formed by two methods. In a first method of forming the lower isolation pattern, a lower isolation layer is formed on an entire surface of the semiconductor substrate where the first and second trenches are formed, and then, a photoresist pattern is formed on the first region of the semiconductor substrate having the lower isolation layer formed thereon, leaving the second region exposed. The lower isolation layer in the second region is etched, using the photoresist pattern as an etch mask, to expose at least an upper sidewall of the second trench. After removing the photoresist pattern, the remaining lower isolation layer is etched to expose an upper sidewall of the first trench and simultaneously to form a lower isolation pattern for filling a lower region of the first trench.
In another method of forming the lower isolation pattern, a lower isolation layer is formed on an entire surface of the semiconductor substrate where the first and second trenches are formed, and then, the lower isolation layer is etched to form a lower isolation pattern in the lower region of the first trench. A photoresist pattern is formed on the first region of the semiconductor substrate having the lower isolation pattern formed thereon, leaving the second region exposed. The lower isolation layer remaining in the second region is removed using the photoresist pattern as an etch mask, and then, the photoresist pattern is removed.
In either of these methods, the lower isolation layer is preferably formed from an SOG layer. Additionally, the lower isolation layer is etched preferably by a wet etch, a dry etch or a mixture of both. After forming the lower isolation pattern, a thermal oxidation process (e.g., a curing process) is preferably performed to densify the lower isolation pattern.
In order to form an upper isolation pattern, an upper isolation layer is formed on an entire surface of the semiconductor substrate that results after forming the lower isolation pattern, and then, the upper isolation layer is planarized to expose a top surface of the semiconductor substrate. A chemical mechanical polishing (CMP) process is preferably used to planarize the upper isolation layer. Also, the upper isolation layer is preferably formed of at least one of an HDP oxide or a USG layer.
Another embodiment of the present invention is directed to a structure of trench isolation, in which an SOG pattern is left only in a lower region of a trench that has a high aspect ratio and cannot be easily buried using a conventional method. The structure of trench isolation includes a first trench and a second trench that are formed in a first region and a second region of a semiconductor substrate, respectively; a lower isolation pattern fills a lower region of the first trench while exposing an upper sidewall of the first trench; and an upper isolation pattern fills the second trench and an upper region of the first trench.
Inner walls of the first and second trenches are preferably covered by a nitride liner pattern. Preferably, the lower isolation pattern is formed of an SOG layer, and the upper isolation pattern is formed of at least one of an HDP oxide layer and a USG layer.